A. Technical Field
The present invention relates generally to signal processing, and more particularly, to the management of a serial communication link between two components, such as a serializer/deserializer (“SERDES”) and a transceiver.
B. Background of the Invention
In a communication device, data can be transmitted from one component to another component by a serial or parallel data transfer. With the rapid improvement in networking technologies, there is a great demand for high speed component-to-component communication rates in order to move larger amounts of data more efficiently within a networking device.
High-speed serial links are being interfaced between networking components to achieve these communication rate increases. The actual data rates on these links may be defined by various protocols and standards, such as the System Packet Interface Level 4 (SPI-4) protocol that covers a spectrum of 622 Mb/s to rates above 1 Gb/s.
A SERDES may interface a parallel data bus with a serial link by effectively serializing or deserializing a data signal. SERDES technology has become very important as data rates have continually increased because a very fast serial link may be converted to a deserialized signal that can be more easily transmitted and processed on a parallel data bus.
FIG. 1 illustrates an exemplary SERDES and interfacing component(s) according to one embodiment of the invention. In this particular example, a SERDES 101 interfaces either a 64 or 128 bit parallel bus 103 to a serial data link 105. The serial data link 105 is also coupled to a transceiver 102. In the operation of a system, the rate of the system core logic may operate at a different rate than the serial data link 105 because of the parallel transfer of data to the core logic.
In one example, the SERDES 101 serial interface receives an 8-bit data stream clocked at 500 MHz and forwards the data to the core logic in a 16-bit data stream clocked at 250 MHz. The clock difference between the SERDES 101 interface and the system core logic may be synthesized and mapped to a structure such as an ASIC or FPGA located within the data path to compensate for this clock mismatch. However, if the same serial interface on the SERDES 101 receives an 8-bit data stream clocked at 1 GHz, then the system core logic needs to be clocked at 500 MHz to properly process a corresponding 16-bit data stream.
Current ASIC and FPGA technology is unable to cost effectively provide an ASIC or FPGA that achieves the required clocking speed of 500 MHz or above for core logic processing. In order to increase the required data rate at the system core logic, the width of the parallel data bus may be expanded by a factor of two. Consequently, in this particular example, the parallel data bus may be expanded to 64-bit or wider to reduce the required internal core logic clocking speed.
The principle of expanding parallel data bus width may be extrapolated to achieve higher data rates without having to increase a corresponding clocking speed. For example, the 64-bit parallel bus could be changed to a 128-bit or 256-bit to reduce the clock frequency of 500 MHz to half or one-fourth respectively.
One current solution in which variable width data buses are provided is by generating multiple system design versions in which different inputs and clock frequencies are associated with each clocking speed and input. However, creating multiple version of a system design may become logistically difficult because of the creation and maintenance of multiple source codes related to the design. Further, the verification environment and process may become overly complicated which may require support engineers to update patches for multiple customers using different versions of the system design.
Therefore there is a need for providing a single system design that allows multiple parallel data widths and clock inputs in order to facilitate the speed matching of a component, such as core logic, to the serial interface of a SERDES or other component.